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Coarse-grained reconfigurable array

A coarse-grained reconfigurable array or coarse-grained reconfigurable architecture (CGRA) is a class of spatial computing hardware built from a relatively large number of processing elements (PEs) connected through a programmable, statically or dynamically reconfigurable on-chip interconnect. By reconfiguring both the operation of each PE and the routing between PEs, a CGRA can be specialized to implement the dataflow graph of a computation, most often the body of a performance-critical loop. It sits between the adaptability of software-programmable processors and the energy efficiency of custom hardware.

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A coarse-grained reconfigurable array or coarse-grained reconfigurable architecture (CGRA) is a class of spatial computing hardware built from a relatively large number of processing elements (PEs) connected through a programmable, statically or dynamically reconfigurable on-chip interconnect. By reconfiguring both the operation of each PE and the routing between PEs, a CGRA can be specialized to implement the dataflow graph of a computation, most often the body of a performance-critical loop. It sits between the adaptability of software-programmable processors and the energy efficiency of custom hardware.123

Log-scale plot of energy efficiency against flexibility for hardware classes, with ASICs most efficient but least flexible, CPUs least efficient but most flexible, and CGRAs highlighted near the efficient, low-flexibility end.
Energy efficiency (MOPS/mW, log scale) versus flexibility for the principal hardware classes. Efficiency and flexibility trade off against each other, and CGRAs (highlighted) sit toward the ASIC end of the efficiency scale while remaining considerably more flexible.1 source ↗

The building blocks of a CGRA are fixed at the word level and reconfigured at a coarse granularity, distinguishing it from a field-programmable gate array (FPGA). FPGAs are reconfigurable at the level of individual bits and logic gates, which yields great flexibility at the cost of increased area, power, and configuration time overheads. General-purpose processors (CPUs and GPUs) are also highly flexible, but pay the energy cost of fetching and decoding an instruction stream for every operation, whereas an application-specific integrated circuit (ASIC) is the most energy-efficient option precisely because it is specialized to a single application and therefore the least flexible. By operating at word granularity, a CGRA retains much of the spatial, energy-efficient parallelism of custom hardware while remaining reprogrammable in software.1

CGRAs were first envisioned in 1960 and took their modern shape in the mid-1990s.4 Since then, they have been applied to signal processing, wireless communication, and machine learning, and they appear in both academic prototypes and commercial silicon. Running a program on a CGRA depends on a specialized compiler that maps the program’s dataflow graph onto the array, a step that remains one of the main obstacles to wider adoption.5

Background

Interest in CGRAs comes from a widening gap in the hardware landscape. As the end of Dennard scaling and the slowing of Moore’s law reduce the performance gains that general-purpose processors once delivered automatically, computer architecture turned toward specialization to keep improving performance per watt, pushed in part by demanding workloads such as neural networks. At one extreme, fixed-function ASICs achieve the highest efficiency but incur high non-recurring engineering costs and cannot be changed after fabrication. At the other end, von Neumann processors are fully programmable but energy-inefficient, with FPGAs sitting in a flexible but costly middle ground. As dataflow architecture is reconfigurable at the word level, CGRAs try to combine near-ASIC efficiency with post-fabrication programmability.1

History

The idea of a machine whose structure can be reconfigured for a computation dates to the "fixed-plus-variable structure computer" proposed by Gerald Estrin in 1960.4 Coarse-grained arrays in the modern sense emerged in the mid-1990s, when several groups replaced the bit-level cells of an FPGA with word-level processing elements.5 The KressArray introduced a two-dimensional mesh of reconfigurable datapath units; MATRIX combined a word-level datapath with a configurable interconnect; RaPiD and PipeRench organized their cells as reconfigurable pipelines, with PipeRench reaching silicon; and MorphoSys paired a reconfigurable-cell mesh with a control processor for data-parallel media workloads.6

Through the 2000s, the designs grew larger and more tightly integrated. ADRES coupled a VLIW processor with a reconfigurable matrix; TRIPS explored a polymorphous array capable of exploiting instruction-, thread-, and data-level parallelism; and PACT XPP offered a self-reconfiguring commercial fabric.789 From the 2010s onward, research emphasized data movement and system integration: HyCUBE introduced a single-cycle multi-hop interconnect, Plasticine organized computation around pattern compute and pattern memory units, and the stream-dataflow (Softbrain) model decoupled memory streaming from the spatial datapath.101112 The same period saw an open-source ecosystem take shape, including ultra-low-power edge arrays such as OpenEdgeCGRA, which is integrated with the X-HEEP RISC-V microcontroller in the HEEPsilon platform to give a complete flow from C code to hardware.1314

A handful of CGRAs have reached commercial silicon. Samsung’s Reconfigurable Processor (SRP), derived from ADRES, has appeared in systems-on-chip and in ultra-low-power biomedical variants;1516 SambaNova commercialized its reconfigurable dataflow unit (RDU), a large dataflow accelerator built from pattern compute and pattern memory units and aimed at machine-learning training and inference.17

Architecture

A CGRA fabric is typically organized as a two-dimensional array of processing elements, each built around an arithmetic logic unit (ALU) or functional unit, a small local register file or set of pipeline registers, and one or more configuration registers that determine, on a per-PE basis, which operation to execute and how operands are routed. The PEs are connected by a programmable interconnect (commonly a mesh, a torus, or, for smaller arrays, a crossbar switch) that lets operands produced by one PE reach its neighbors or, in richer designs, more distant PEs. Most CGRAs are not standalone; the array is coupled to a host or control processor, a role historically filled by a VLIW or ARM core and, in many recent open-source designs, by a RISC-V core. Depending on how closely the array is bound to the host, a CGRA is described as tightly coupled, sitting inside the processor datapath and invoked as a custom instruction, or loosely coupled, acting as a separate accelerator that communicates over an on-chip interconnect. The loosely coupled arrangement is the more common one in larger modern systems.18

Three-panel schematic showing a controller-driven array attached to memory, a mesh of interconnected processing elements fed by a data manager, and the interior of one processing element with a functional unit, local memory and a crossbar.
A CGRA at three levels of detail: the array driven by a controller and coupled to memory (left), the mesh of processing elements fed by a data manager (center), and the internals of one PE, namely its functional unit, local memory, and crossbar interconnect (right). source ↗

Programming a CGRA means loading a configuration into the array’s configuration memory: for each PE, the configuration specifies its operation (for example, add, multiply, shift, or compare) and the routing of its inputs and outputs. Because this configuration is coarse-grained, a dedicated CGRA can switch to a new configuration in nanoseconds, orders of magnitude faster than an FPGA can reconfigure. A single configuration yields a single spatial "snapshot" of the dataflow graph (DFG) being executed. In spatial-only CGRAs, the DFG of a kernel is unrolled once across the array, and each PE keeps the same configuration for the whole execution, similar in spirit to a systolic array. In temporal or spatio-temporal CGRAs, each PE instead cycles through a short sequence of configurations held in local configuration memory, time-multiplexing several DFG nodes onto the same physical PE across successive cycles.125

The literature further classifies CGRA execution by the number of configurations and data streams a PE array handles at once: single-configuration, single-data (SCSD); single-configuration, multiple-data (SCMD), in which one configuration is applied across the array; and multiple-configuration, multiple-data (MCMD), in which several distinct configurations run concurrently.1

Comparison of CGRAs with other computing architectures
Architecture Flexibility Computation form Execution mechanism
Temporal Spatial Reconfiguration time Configuration-driven Dataflow-driven Instruction-driven
CGRA Domain Yes Yes ns–μs Yes Yes No
AI engine (a) Domain Yes Yes ns–μs Yes Yes Yes
FPGA General No(1) Yes ms–s Yes Yes No
ASIC Fixed No Yes No No(2) Yes No
CPU General Yes Yes N/a No No Yes
GPU General Yes Yes N/a No No Yes
Multi-core processor General Yes No N/a No Yes Yes

Notes:

  • (a) "AI engine" here denotes a domain-specific AI/ML accelerator built as a spatial array of VLIW-SIMD vector tiles connected by a programmable AXI-stream interconnect and local memories (for example, the AMD/Xilinx Versal AI Engine). Unlike an FPGA or a CGRA fabric, the AI-engine array and each tile’s datapath are fixed at the time of fabrication. What is programmable at run time is the software executed by each tile (so it is instruction-driven) and the stream and dataflow connectivity between tiles (so it is configuration- and dataflow-driven).19
  • (1) FPGAs can perform temporal computation, but doing so is not practical given the overhead involved.
  • (2) ASICs do not support reconfiguration, although configuration codes may still exist.
  • The reconfiguration-time entry is marked "not applicable" for CPUs, GPUs, and multi-core processors, since these are instruction-driven machines that do not reconfigure a fabric; their per-operation latency reflects instruction issue, not reconfiguration.
A two-by-two chart plotting PE composition, from homogeneous to heterogeneous, against execution model, from spatial-only to spatio-temporal, with difficulty increasing toward the top-right corner.
The two-dimensional CGRA design space: PE composition (homogeneous ↔ heterogeneous) against execution model (spatial-only ↔ spatio-temporal). Specialization and mapping difficulty increase toward the top-right. source ↗

A further architectural distinction concerns whether the PEs across the array are identical or specialized. In a homogeneous CGRA, every PE supports the same set of operations, which simplifies placement and routing during compilation. In a heterogeneous CGRA, the PEs are specialized (for instance, only some implement a multiplier or a memory load/store unit, while the rest handle simpler arithmetic and logic operations). This reduces area and power for a given target workload, but at the cost of a harder mapping problem, since the compiler must place each operation on a PE that actually supports it. The homogeneous-versus-heterogeneous axis is independent of the spatial-versus-spatio-temporal distinction, giving a two-dimensional design space that runs from simple, easy-to-compile homogeneous-spatial arrays to complex, highly specialized heterogeneous-spatio-temporal ones.20

Programming and compilation

Flowchart running from source code to a dataflow graph, then scheduling and place-and-route onto the array, producing a configuration, with a feedback arrow that raises the initiation interval when mapping fails.
Typical CGRA compilation flow: source code is reduced to a dataflow graph, which is scheduled and placed-and-routed onto the array to produce a configuration. On mapping failure the initiation interval (II) is increased and the kernel re-mapped. source ↗

Because a CGRA executes a spatial dataflow graph rather than a sequential instruction stream, its compiler must turn a program into a placed-and-routed configuration rather than into machine instructions. A typical flow starts from a high-level language, usually C or C++, identifies the performance-critical loops, and lowers each of them to a dataflow graph, commonly through an LLVM-based front end, despite some novel methodology uses MLIR2122. Loops that contain conditionals are made spatial by converting control dependencies into data dependencies through predication, whether partial or full, so that both sides of a branch are computed, and the correct result is then selected.1

The core of the flow is the mapping problem: binding each DFG node to a PE and routing every data dependency through the interconnect, subject to the PEs’ operational capabilities, the interconnect topology, and timing constraints. This problem is NP-complete and is usually split into two coupled sub-problems: scheduling, which assigns each operation a time slot, and placement-and-routing, which binds operations to PEs and reserves interconnect resources. For pipelined loops, the key quality metric is the initiation interval (II), the number of cycles between the start of successive loop iterations, which sets the throughput. Software pipelining by modulo scheduling searches for a valid mapping at the smallest achievable II, raising the II and rescheduling whenever mapping fails. Mappers described in the literature use heuristics, simulated annealing, integer linear programming, graph-theoretic formulations such as maximal-clique search, and, more recently, learning-based and hierarchical methods.2324

Selected open-source CGRA design and compilation frameworks
Framework First release Origin Input / front end Mapping RTL generation Simulation Distinguishing features
CGRA-ME2526 2017 (v2.0, 2024) University of Toronto C via LLVM; custom architecture description Architecture-adaptive; ILP and simulated annealing Verilog Yes (from v2.0) Models homogeneous spatio-temporal CGRAs; limited handling of control divergence
CCF 2018 Arizona State University C with #pragma CGRA (Clang/LLVM) Graph-based; partial predication No Cycle-accurate (gem5, CPU + CGRA) CPU-coupled accelerator; MiBench, Parboil and Rodinia benchmarks
OpenCGRA / CGRA-Flow27 2021 Pacific Northwest National Laboratory / Northeastern University C/C++ loop; optional GUI Operation-centric; supports control divergence, recurrences, multidimensional loops Verilog (FPGA-synthesizable) Yes (user-provided test benches) GUI front end (CGRA-Flow); parameterizable interconnect generator
Morpher 2022 National University of Singapore C via LLVM Architecture-adaptive; heuristic, simulated annealing, and learning-based (LISA) Yes (via Pillars/Chisel) Cycle-accurate with automated validation Learning-based (LISA) mapping; automated validation flow

These frameworks differ mainly along four axes: whether they generate a DFG automatically from source or require the user to supply one; whether their mapper is architecture-adaptive (able to retarget a new interconnect or PE mix without code changes); whether they emit synthesizable RTL; and whether they include an integrated cycle-accurate simulator. Comparative studies typically report the achievable initiation interval, mapping success rate, and compilation time across standard loop-kernel benchmark suites such as PolyBench.28

Challenges

Despite their efficiency advantages, CGRAs remain an open research question, with limitations in programmability and productivity yet to be solved.12

Mapping and scheduling

Mapping a kernel’s dataflow graph onto the array and routing its dependencies through the interconnect is a hard combinatorial problem. The compiler must simultaneously satisfy PE-capability, routing/adjacency, and timing constraints, and the difficulty compounds when the PEs are heterogeneous or the interconnect topology is irregular. A mapping that succeeds for one kernel may fail for a slightly different one on the same fabric.2

Control flow

CGRAs map most naturally onto affine, loop-dominated, data-parallel kernels expressed as dataflow graphs. Irregular control flow, such as data-dependent branches, function calls, and pointer chasing, does not translate cleanly onto a spatial fabric, whether that fabric is statically or dynamically scheduled, and handling it efficiently remains an active research problem.29

Configuration memory overhead

Temporal and spatio-temporal designs need sufficient on-chip configuration (context) memory to hold every configuration a PE cycles through.1 Keeping several distinct configurations resident at once (the multiple-configuration, multiple-data, or MCMD, execution model) costs more of this memory than sharing a single configuration across the array, as in the single-configuration, multiple-data (SCMD) model. That capacity translates directly into area and power, a cost that must be weighed against the execution model a given workload actually needs.1

Toolchain fragmentation

Unlike CPUs and GPUs, CGRAs have no standard, widely adopted compiler or hardware-description ecosystem. Most academic and industrial designs still rely on bespoke, architecture-specific toolchains, which limit reproducibility and slow adoption beyond the group that built a given fabric.127

Applications

CGRAs are best suited to compute-intensive, loop-dominated kernels with regular dataflow, and their application history reflects this.3 Early arrays targeted digital signal processing, multimedia, and image and video processing, where the same operations are applied to streams of data. Related work applied them to wireless baseband and software-defined radio, using reconfigurability to switch between standards.1

More recently, the dominant driver has been machine learning.3 CGRAs and CGRA-like dataflow accelerators are used for deep neural network inference and training, from large commercial systems that run transformer and large-language-model workloads down to ultra-low-power arrays at the edge. Other domains include scientific and high-performance computing, embedded bio-signal processing for wearable and near-sensor devices,30 and error-tolerant workloads addressed through approximate computing variants that trade accuracy for energy.31

Notable implementations

The following table lists representative CGRA and CGRA-like designs from academia and industry, spanning the eras described in the History section.

Representative CGRA implementations
System Year Origin Type Notable for
RaPiD32 1996 University of Washington Academic Linear, pipelined reconfigurable datapath
ADRES7 2003 IMEC Academic VLIW host tightly coupled to a reconfigurable matrix
PACT XPP9 2003 PACT XPP Technologies Commercial Self-reconfiguring dataflow fabric
TRIPS8 2004 University of Texas at Austin Academic Polymorphous array (ILP/TLP/DLP)
Samsung SRP15 2010s Samsung Commercial ADRES-derived; used in systems-on-chip
DySER33 2012 University of Wisconsin–Madison Academic Reconfigurable array embedded in a processor pipeline
HyCUBE10 2017 National University of Singapore Academic Single-cycle multi-hop interconnect
Plasticine11 2017 Stanford University Academic Pattern compute and pattern memory units
Renesas DRP34 2018 Renesas Commercial Dynamically reconfigurable processor for embedded AI
SambaNova RDU17 2021 SambaNova Commercial Plasticine-derived AI dataflow accelerator
OpenEdgeCGRA14 2023 EPFL Academic Resizable ultra-low-power edge array (HEEPsilon / X-HEEP)
UbitiumCGRA35 2026 Ubitium Commercial First CGRA to run Linux without a processor as controller
See also

See also

References

References

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